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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. AD8007/ad8008 ultralow distortion high speed amplifiers features extremely low distortion second harmonic ?8 dbc @ 5 mhz ?3 dbc @ 20 mhz (AD8007) ?7 dbc @ 20 mhz (ad8008) third harmonic ?01 dbc @ 5 mhz ?2 dbc @ 20 mhz (AD8007) ?8 dbc @ 20 mhz (ad8008) high speed 650 mhz, ? db bandwidth (g = +1) 1000 v/ s slew rate low noise 2.7 nv/ hz input voltage noise 22.5 pa/ hz input inverting current noise low power 9 ma/amplifier typ supply current wide supply voltage range 5 v to 12 v 0.5 mv typical input offset voltage small packaging soic-8, msop, and sc70 packages available applications instrumentation if and baseband amplifiers filters a/d drivers dac buffers connection diagrams general description the AD8007 (single) and ad8008 (dual) are high perfor- mance current feedback amplifiers with ultralow distortion and noise. unlike other high performance amplifiers, the low price and low quiescent current allow these amplifiers to be used in a wide range of applications. adi? proprietary second generat ion extra-fast complementary bipolar (xfcb) process enables such high performance amplifiers with low power consumption. the AD8007/ad8008 have 650 mhz bandwidth, 2.7 nv/ hz voltage noise, ?3 db sfdr @ 20 mhz (AD8007), and ?7 dbc sfdr @ 20 mhz (ad8008). with the wide supply voltage range (5 v to 12 v) and wide band- width, the AD8007/ad8008 are designed to work in a variety of applications. the AD8007/ad8008 amplifiers have a low power supply current of 9 ma/amplifier. the AD8007 is available in a tiny sc70 package as well as a standard 8-lead soic. the dual ad8008 is available in both 8-lead soic and 8-lead msop packages. these amplifiers are rated to work over the industrial temperature range of ?0 c to +85 c. frequency ?mhz ?0 ?0 ?10 1 100 10 distortion ?dbc ?0 ?0 ?0 ?00 ?0 ?0 third g = +2 r l = 150 v s = 5v v out = 2v p-p second figure 1. AD8007 second and third harmonic distortion vs. frequency soic (r) sc70 (ks-5) 8 7 6 5 1 2 3 4 nc = no connect nc ?n +in nc +v s v out nc ? s AD8007 (top view) 5 1 2 3 ?n +in +v s v out ? s 4 AD8007 (top view) soic (r) and msop (rm) 1 v out1 ?n1 + in1 ? s +v s v out2 ?n2 + in2 8 27 36 45 ad8008 (top view)
rev. d e2e AD8007/ad8008especifications (@ t a = 25 c, r s = 200 , r l = 150 , r f = 499 , gain = +2, unless otherwise noted.) AD8007/ad8008 parameter conditions min typ max unit dynamic performance e3 db bandwidth g = +1, v o = 0.2 v p-p, r l = 1 k 540 650 mhz g = +1, v o = 0.2 v p-p, r l = 150 250 500 mhz g = +2, v o = 0.2 v p-p, r l = 150 180 230 mhz g = +1, v o = 2 v p-p, r l = 1 k 200 235 mhz bandwidth for 0.1 db flatness v o = 0.2 v p-p, g = +2, r l = 150 50 90 mhz overdrive recovery time 2.5 v input step, g = +2, r l = 1 k 30 ns slew rate g = +1, v o = 2 v step 900 1000 v/ s settling time to 0.1% g = +2, v o = 2 v step 18 ns settling time to 0.01% g = +2, v o = 2 v step 35 ns noise/harmonic performance second harmonic f c = 5 mhz, v o = 2 v p-p e88 dbc f c = 20 mhz, v o = 2 v p-p e83/e77 dbc third harmonic f c = 5 mhz, v o = 2 v p-p e101 dbc f c = 20 mhz, v o = 2 v p-p e92/e98 dbc imd f c = 19.5 mhz to 20.5 mhz, r l = 1 k , v o = 2 v p-p e77 dbc third order intercept f c = 5 mhz, r l = 1 k 43.0/42.5 dbm f c = 20 mhz, r l = 1 k 42.5 dbm crosstalk (ad8008) f = 5 mhz, g = +2 e68 db input voltage noise f = 100 khz 2.7 nv/ hz input current noise einput, f = 100 khz 22.5 pa/ hz +input, f = 100 khz 2 pa/ hz differential gain error ntsc, g = +2, r l = 150 0.015 % differential phase error ntsc, g = +2, r l = 150 0.010 degree dc performance input offset voltage 0.5 4 mv input offset voltage drift 3 v/ c input bias current +input 4 8 a einput 0.4 6 a input bias current drift +input 16 na/ c einput 9 na/ c transimpedance v o = 2.5 v, r l = 1 k 1.0 1.5 m r l = 150 0.4 0.8 m input characteristics input resistance +input 4 m input capacitance +input 1 pf input common-mode voltage range e3.9 to +3.9 v common-mode rejection ratio v cm = 2.5 v 56 59 db output characteristics output saturation voltage v cc e v oh , v ol e v ee , r l = 1 k 1.1 1.2 v short circuit current, source 130 ma short circuit current, sink 90 ma capacitive load drive 30% overshoot 8 pf power supply operating range 5 12 v quiescent current per amplifier 9 10.2 ma power supply rejection ratio +psrr 59 64 db epsrr 59 65 db v s = 5 v
rev. d AD8007/ad8008 e3e (@ t a = 25 c, r s = 200 , r l = 150 , r f = 499 , gain = +2, unless otherwise noted.) AD8007/ad8008 parameter conditions min typ max unit dynamic performance e3 db bandwidth g = +1, v o = 0.2 v p-p, r l = 1 k 520 580 mhz g = +1, v o = 0.2 v p-p, r l = 150 350 490 mhz g = +2, v o = 0.2 v p-p, r l = 150 190 260 mhz g = +1, v o = 1 v p-p, r l = 1 k 270 320 mhz bandwidth for 0.1 db flatness vo = 0.2 v p-p, g = +2, r l = 150 72 120 mhz overdrive recovery time 2.5 v input step, g = +2, r l = 1 k 30 ns slew rate g = +1, v o = 2 v step 665 740 v/ s settling time to 0.1% g = +2, v o = 2 v step 18 ns settling time to 0.01% g = +2, v o = 2 v step 35 ns noise/harmonic performance second harmonic f c = 5 mhz, v o = 1 v p-p e96/e95 dbc f c = 20 mhz, v o = 1 v p-p e83/e80 dbc third harmonic f c = 5 mhz, v o = 1 v p-p e100 dbc f c = 20 mhz, v o = 1 v p-p e85/e88 dbc imd f c = 19.5 mhz to 20.5 mhz, r l = 1 k , e89/e87 dbc v o = 1 v p-p third order intercept f c = 5 mhz, r l = 1 k 43.0 dbm f c = 20 mhz, r l = 1 k 42.5/41.5 dbm crosstalk (ad8008) output to output f = 5 mhz, g = +2 e68 db input voltage noise f = 100 khz 2.7 nv/ hz input current noise einput, f = 100 khz 22.5 pa/ hz +input, f = 100 khz 2 pa/ hz dc performance input offset voltage 0.5 4 mv input offset voltage drift 3 v/ c input bias current +input 4 8 a einput 0.7 6 a input bias current drift +input 15 na/ c einput 8 na/ c transimpedance v o = 1.5 v to 3.5 v, r l = 1 k 0.5 1.3 m r l = 150 0.4 0.6 m input characteristics input resistance +input 4 m input capacitance +input 1 pf input common-mode voltage range 1.1 to 3.9 v common-mode rejection ratio v cm = 1.75 v to 3.25 v 54 56 db output characteristics output saturation voltage v cc e v oh , v ol e v ee , r l = 1 k 1.05 1.15 v short circuit current, source 70 ma short circuit current, sink 50 ma capacitive load drive 30% overshoot 8 pf power supply operating range 5 12 v quiescent current per amplifier 8.1 9 ma power supply rejection ratio +psrr 59 62 db epsrr 59 63 db v s = 5 v
rev. d e4e AD8007/ad8008 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8007/ad8008 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . see figure 2 common-mode input voltage . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . 1.0 v output short circuit duration . . . . . . . . . . . . . . see figure 2 storage temperature . . . . . . . . . . . . . . . . . . e65 c to +125 c operating temperature range . . . . . . . . . . . e40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum power dissipation the maximum safe power dissipation in the AD8007/ad8008 packages is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die will locally reach the junction temperature. at approximately 150 c, which is the glass transition tem perature, the plastic will change its proper- ties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, perma- nently shifting the parametric performance of the AD8007/ ad8008. exceeding a junction temperature of 175 c for an extended period of time can result in changes in the silicon devices, potentially causing failure. the still-air thermal properties of the package and pcb ( j a ), ambient temperature ( t a ), and the total power dissipated in the package ( p d ) determine the junction temperature of the die. the junction temperature can be calculated as follows: tt p ada jj =+ () the power dissipated in the package ( p d ) is the sum of the quies- cent pow er dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins ( v s ) times the quiescent current ( i s ). assuming the load ( r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is dissipated in the package and some in the load ( v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p d = quiescent power + (total drive power e load power): pvi vv r v r dss s out l out l = () + ? 2 2 rms output voltages should be considered. if r l is referenced to v s , as in single-supply operation, then the total drive power is v s i out . if the rms signal levels are indeterminate, then consider the worst case, when v out = v s / 4 for r l to midsupply: pvi v r dss s l = () + 4 2 in single-supply operation, with r l referenced to v s , worst case is v v out s = 2 airflow will increase heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the ja . care must be taken to minimize parasitic capaci- tances at the input leads of high speed op amps as discussed in the board layout section. figure 2 shows the maximum safe power dissipation in the pack- age versus ambient temperature for the soic-8 (125 c/w), m sop (150 c/w), and sc70 (210 c/w) packages on a jedec standard 4-layer board. ja values are approximations. ambient temperature e c 2.0 1.5 0 e60 100 e40 maximum power dissipation e w e20 0 20 4 06080 1.0 0.5 soic-8 sc70-5 msop-8 figure 2. maximum power dissipation vs. temperature for a 4-layer board output short circuit shorting the output to ground or drawing excessive current for the AD8007/ad8008 will likely cause catastrophic failure.
rev. d AD8007/ad8008 ? ordering guide package model temperature range description package outline branding AD8007ar ?0 c to +85 c 8-lead soic r-8 AD8007ar-reel ?0 c to +85 c 8-lead soic r-8 AD8007ar-reel7 ?0 c to +85 c 8-lead soic r-8 AD8007aks-r2 ?0 c to +85 c 5-lead sc70 ks-5 hta AD8007aks-reel ?0 c to +85 c 5-lead sc70 ks-5 hta AD8007aks-reel7 ?0 c to +85 c 5-lead sc70 ks-5 hta ad8008ar ?0 c to +85 c 8-lead soic r-8 ad8008ar-reel7 ?0 c to +85 c 8-lead soic r-8 ad8008ar-reel ?0 c to +85 c 8-lead soic r-8 ad8008arm ?0 c to +85 c 8-lead msop rm-8 h2b ad8008arm-reel ?0 c to +85 c 8-lead msop rm-8 h2b ad8008arm-reel7 ?0 c to +85 c 8-lead msop rm-8 h2b
rev. d e6e AD8007/ad8008etypical performance characteristics frequency e mhz 3 2 e5 1 100 10 normalized gain e db e1 e2 e3 e4 1 0 e6 e7 1000 g = +1 g = +2 g = +10 g = e1 tpc 1. small signal frequency response for various gains frequency e mhz 3 2 e5 100 10 gain e db e1 e2 e3 e4 1 0 e6 e7 1000 r l = 150 , v s = +5v r l = 150 , v s = 5v r l = 1k , v s = 5v g = +1 tpc 2. small signal frequency response for v s and r load frequency e mhz 3 2 e5 100 10 gain e db e1 e2 e3 e4 1 0 e6 e7 1000 r s = 249 r s = 301 r s = 200 g = +1 r l = 1k tpc 3. small signal frequency response for various r s values frequency e mhz 6.4 6.3 5.6 100 10 gain e db 6.0 5.9 5.8 5.7 6.2 6.1 5.5 5.4 1000 g = +2 v s = +5v v s = 5v tpc 4. 0.1 db gain flatness; v s = +5, 5 v frequency e mhz 9 8 1 100 10 gain e db 5 4 3 2 7 6 0 e1 1000 g = +2 r l = 150 v s = +5v r l = 150 , v s = 5v r l = 1k , v s = 5v r l = 1k , v s = +5v tpc 5. small signal frequency response for v s and r load frequency e mhz 9 8 1 100 10 gain e db 5 4 3 2 7 6 0 e1 1000 g = +2 r f = r g = 249 r f = r g = 324 r f = r g = 649 r f = r g = 499 tpc 6. small signal frequency response for v arious feedback resistors, r f =r g (v s = 5 v, r l = 150 , r s = 200 , r f = 499 , unless otherwise noted.)
rev. d AD8007/ad8008 e7e frequency e mhz 10 9 2 1 100 10 gain e db 6 5 4 3 8 7 1 0 1000 g = +2 20pf 0pf 20pf and 10 snub 20pf and 20 snub 499 499 200 49.9 r snub c load tpc 7. small signal frequency response for capacitive load and snub resistor frequency e mhz 3 2 e5 100 10 gain e db e1 e2 e3 e4 1 0 e6 e7 1000 v s = +5v, +85 c v s = 5v, e40 c v s = +5v, e40 c v s = 5v, +85 c g = +1 tpc 8. small signal frequency response over temperature, v s = +5 v, 5 v frequency e mhz 3 2 e5 1 100 10 normalized gain e db e1 e2 e3 e4 1 0 e6 e7 1000 v out = 2v p-p g = +1 g = +2 g = +10 g = e1 tpc 9. large signal frequency response for various gains frequency e hz 10m 1m 10k 1m 100k transimpedance e 1k 100 10 1 100k 10k 10m 100m 1g 0 e30 e90 e150 e210 e270 e330 phase e degrees 2g transimpedance phase 30 90 e180 tpc 10. transimpedance and phase vs. frequency frequency e mhz 9 8 1 100 10 gain e db 5 4 3 2 7 6 0 e1 1000 g = +2 v s = +5v, +85 c v s = 5v, e40 c v s = +5v, e40 c v s = 5v, +85 c tpc 11. small signal frequency response over temperature, v s = +5 v, 5 v frequency e mhz 9 8 1 100 10 gain e db 5 4 3 2 7 6 0 e1 1000 r l = 150 , v s = 5v, v o = 2v p-p r l = 1k , v s = 5v, v o = 2v p-p r l = 150 , v s = +5v, v o = 1v p-p r l = 1k , v s = +5v, v o = 1v p-p g = +2 tpc 12. large signal frequency response for v s and r load
rev. d e8e AD8007/ad8008 frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 g = 1 v s = 5v v o = 1v p-p hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 13. AD8007 second and third harmonic distortion vs. frequency and r l frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 g = 1 v s = 5v v o = 2v p-p hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 14. AD8007 second and third harmonic distortion vs. frequency and r l frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 v s = 5v v o = 2v p-p r l = 150 hd2, g = 1 hd3, g = 1 hd2, g = 10 hd3, g = 10 e30 tpc 15. AD8007 second and third harmonic distortion vs. frequency and gain frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 g = 2 v s = 5v v o = 1v p-p hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 16. AD8007 second and third harmonic distortion vs. frequency and r l frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 g = 2 v s = 5v v o = 2v p-p hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 17. AD8007 second and third harmonic distortion vs. frequency and r l frequency e mhz e90 10 1 distortion e dbc e50 e60 e70 e80 e40 e100 e110 100 g = +2 v s = 5v r l = 150 e30 hd2, v o = 2v p-p hd3, v o = 2v p-p hd2, v o = 4v p-p hd3, v o = 4v p-p tpc 18. AD8007 second and third harmonic distortion vs. frequency and v out
rev. d AD8007/ad8008 e9e frequency e mhz 100 10 hd2, r l = 1k hd2, r l = 150 hd3, r l = 1k hd3, r l = 150 g = 1 v s = 5v v o = 1v p-p e40 1 distortion e dbc e110 e100 e90 e80 e70 e60 e50 tpc 19. ad8008 second and third harmonic distortion vs. frequency and r l frequency e mhz e40 1 100 10 distortion e dbc hd2, r l = 1k hd2, r l = 150 hd3, r l = 1k hd3, r l = 150 g = 1 v s = 5v v o = 1v p-p e110 e100 e90 e80 e70 e60 e50 tpc 20. ad8008 second and third harmonic distortion vs. frequency and r l frequency e mhz 100 10 hd2, g = 10 v s = 5v v o = 2v p-p r l = 150 hd2, g = 1 hd3, g = 1 hd3, g = 10 e40 1 distortion e dbc e110 e100 e90 e80 e70 e60 e50 e30 tpc 21. ad8008 second and third harmonic distortion vs. frequency and gain frequency e mhz 100 10 hd2, r l = 1k hd2, r l = 150 hd3, r l = 1k hd3, r l = 150 g = 2 v s = 5v v o = 1v p-p e40 1 distortion e dbc e110 e100 e90 e80 e70 e60 e50 tpc 22. ad8008 second and third harmonic distortion vs. frequency and r l frequency e mhz 100 10 hd2, r l = 150 hd3, r l = 1k hd3, r l = 150 g = 2 v s = 5v v o = 2v p-p e40 1 distortion e dbc e110 e100 e90 e80 e70 e60 e50 hd2, r l = 1k tpc 23. ad8008 second and third harmonic distortion vs. frequency and r l frequency e mhz 100 10 hd2, v o = 2v p-p g = 2 r l = 150 v s = 5v e40 e110 e100 e90 e80 e70 e60 e50 e30 1 distortion e dbc hd2, v o = 4v p-p hd3, v o = 2v p-p hd3, v o = 4v p-p tpc 24. ad8008 second and third harmonic distortion vs. frequency and v out (v s = 5 v, r s = 200 , r f = 499 , r l = 150 , @ 25 c, unless otherwise noted.)
rev. d e10e AD8007/ad8008 v out e v p-p e90 1.5 1 distortion e dbc e70 e75 e80 e85 e65 2 g = 2 v s = 5v f o = 20mhz 2.5 hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k e60 tpc 25. AD8007 second and third harmonic distortion vs. v out and r l frequency e mhz 38 5 third order intercept e dbm 42 41 40 39 43 g = +2 v s = 5v v o = 2v p-p r l = 1k 37 36 35 10 15 20 25 30 35 40 45 50 55 60 65 70 44 tpc 26. AD8007 third order intercept vs. frequency v out e v p-p e90 1.5 1 e70 e75 e80 e85 e65 2 g = 2 v s = 5v f o = 20mhz 2.5 hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 27. ad8008 second and third harmonic distortion vs. v out and r l v out e v p-p e90 2 1 distortion e dbc e70 e75 e80 e85 e65 34 g = 2 v s = 5v f o = 20mhz e95 e100 e105 e110 56 hd2, r l = 150 hd3, r l = 150 hd2, r l = 1k hd3, r l = 1k tpc 28. AD8007 second and third harmonic distortion vs. v out and r l frequency e mhz 38 42 41 40 39 43 70 44 g = 2 v s = 5v v o = 2v p-p r l = 1k 37 36 35 65 60 55 50 45 40 35 30 25 20 15 10 5 third order intercept e dbm tpc 29. ad8008 third order intercept vs. frequency v out e v p-p e90 1 e70 e75 e80 e85 e65 26 g = 2 v s = 5v f o = 20mhz hd2, r l = 1k hd2, r l = 150 hd3, r l = 150 hd3, r l = 1k e95 e100 e105 e110 345 tpc 30. ad8008 second and third harmonic distortion vs. v out and r l
rev. d AD8007/ad8008 e11e frequency e hz 10 1k 100 vo ltag e noise e nv/ hz 100 10 1 10k 100k 1m 2.7nv/ hz tpc 31. input voltage noise vs. frequency frequency e hz 100k 10m 1m output impedance e 100 10 1 100m 1g 1000 0.1 0.01 g = 2 tpc 32. output impedance vs. frequency frequency e hz 100m 1g cmrr e db e10 e20 e30 100k 1m 0 10m e40 e50 e60 e70 v s = 5v, 5v tpc 33. cmrr vs. frequency frequency e hz 10 10k 100 current noise e pa/ hz 100 10 1 100k 1m 1000 10m 1k noninverting current noise 2.0pa/ hz inverting current noise 22.5pa / hz tpc 34. input current noise vs. frequency frequency e hz 100k 1g crosstalk e db e100 1m 10m 100m e90 e80 e70 e60 e50 e40 e20 e30 g = 2 r = 150 v s = 5v v m = 1v p-p side b driven side a driven tpc 35. ad8008 crosstalk vs. frequency (output to output) frequency e hz 20 10 10k 1m 100k psrr e db e20 e30 e40 e50 0 e10 10m 100m 1g e60 e70 e80 + psrr epsrr tpc 36. psrr vs. frequency (v s = 5 v, r l = 150 , r s = 200 , r f = 499 , unless otherwise noted.)
rev. d e12e AD8007/ad8008 50mv/div g = 1 r l = 150 , v s = 5v and 5v r l = 1k , v s = 5v and 5v 010 20 30 40 50 time e ns tpc 37. small signal transient response for r l = 150 , 1 k and v s = +5 v, 5 v 1v/div g = +1 r l = 150 r l = 1k 01020304050 time e ns tpc 38. large signal transient response for r l = 150 , 1 k g = 2 1v/div 010 20304050 time e ns c load = 0pf c load = 10pf c load = 20pf tpc 39. large signal transient response for capacitive load = 0 pf, 10 pf, and 20 pf g = +2 50mv/div 01020304050 time e ns r l = 150 , v s = +5v and 5v r l = 1k , v s = +5v and 5v tpc 40. small signal transient response for r l = 150 , 1 k and v s = +5 v, 5 v g = e1 1v/div 01020304050 time e ns input output tpc 41. large signal transient response, g = e1, r l = 150 50mv/div c l = 0pf c l = 20pf c l = 20pf r snub = 10 499 499 200 49.9 r snub c load + e g = 2 010 20304050 time e ns tpc 42. small signal transient response: effect of series snub resistor when driving capacitive load
rev. d AD8007/ad8008 e13e 0 100 200 time e ns input (1v/div) r l = 150 r l = 1k output (2v/div) v s v s 300 400 500 g = 2 tpc 43. output overdrive recovery, r l = 1 k , 150 , v in = 2.5 v 0 time e ns 51015202530354045 g = +2 0.1 0 settling time e % 0.2 0.3 0.4 0.5 0.1 0.2 0.3 0.4 0.5 18ns tpc 44. 0.1% settling time, 2 v step r l e e1 200 0 v out e v 3 2 1 0 4 400 600 e2 e3 e4 800 1000 g = +10 v s = 5v v in = 0.75v tpc 45. v out swing vs. r load , v s = 5 v, g = +10, v in = 0.75 v
rev. d e14e AD8007/ad8008 theory of operation the AD8007 (single) and ad8008 (dual) are current feedback amplifiers optimized for low distortion performance. a simplified conceptual diagram of the AD8007 is shown in figure 3. it closely resembles a classic current feedback amplifier comprised of a comple mentary emitter-follower input stage, a pair of signal mir- rors, and a diamond output stage. however, in the case of the AD8007/ ad8008, several modifications have been made to greatly improve the distortion performance over that of a classic current feedback topology. i di e +v s ev s c j 1 c j 2 q1 q2 ine e e e d1 d2 i 1 i 2 in+ i 3 i 4 i do q3 q4 q5 q6 +v s ev s r f out r g m2 m1 hiz figure 3. simplified schematic of AD8007 the signal mirrors have been replaced with low distortion, high precision mirrors. they are shown as m1 and m2 in figure 3. their primary function from a distortion standpoint is to greatly reduce the effect of highly nonlinear distortion caused by capaci- tances c j 1 and c j 2. these capacitors represent the collector-to-base capacitances of the mirrors? output devices. a voltage imbalance arises across the output stage, as measured from the high impedance node hiz to the output node out. this imbalance is a result of delivering high output currents and is the primary cause of output distortion. circuitry is included to sense this output voltage imbalance and generate a compensating current i do . when injected into the circuit, i do reduces the distortion that would be generated at the output stage. similarly, the nonlinear voltage imbalance across the input stage (measured from the noninverting to the inverting input) is sensed, and a current i di is injected to compensate for input-generated distortion. the design and layout are strictly top-to-bottom symmetric in order to minimize the presence of even-order harmonics. using the AD8007/ad8008 supply decoupling for low distortion decoupling for low distortion performance requires careful consideration. the commonly adopted practice of returning the high frequency supply decoupling capacitors to physically sepa- rate (and possibly distant) grounds can lead to degraded even-order harmonic performance. this situation is shown in figure 4 using the AD8007 as an example. note that for a sinu- soidal input, each decoupling capacitor returns to its ground a quasi-rectified current carrying high even-order harmonics. +v s ev s r g 499 r s 200 in r f 499 gnd 1 gnd 2 out AD8007 + + 10 f 10 f 0.1 f 0.1 f figure 4. high frequency capacitors returned to physically separate grounds (not recommended) the decoupling scheme shown in figure 5 is preferable. here, the two high frequency decoupling capacitors are first tied together at a common node, and are then returned to the ground plane through a single connection. by first adding the two currents flowing through each high frequency decoupling capacitor, one is ensuring that the current returned into the ground plane is only at the fundamental frequency. +v s ev s r g 499 r s 200 in r f 499 out AD8007 + + 10 f 0.1 f 10 f 0.1 f figure 5. high frequency capacitors returned to ground at a single point (recommended) whenever physical layout considerations prevent the decoupling scheme shown in figure 5, the user can connect one of the high frequency decoupling capacitors directly across the supplies and connect the other high frequency decoupling capacitor to ground. this is shown in figure 6.
rev. d AD8007/ad8008 e15e +v s ev s r g 499 r s 200 in r f 499 out AD8007 + + 10 f 10 f c1 0.1 f c2 0.1 f figure 6. high frequency capacitors connected across the supplies (recommended) layout considerations the standard noninverting configuration with recommended power supply bypassing is shown in figure 6. the 0.1 f high fre- quency decoupling capacitors should be x7r or npo chip components. connect c2 from the +v s p in to the ev s pin. con- nect c1 from the +v s pin to signal ground. the length of the high frequency bypass capacitor leads is critical. parasitic inductance due to long leads will work against the low impedance created by the bypass capacitor. the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. for the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. layout and grounding considerations grounding a ground plane layer is important in densely packed pc boards to minimize parasitic inductances. however, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. the length of the current path is directly proportional to the magnitude of parasitic induc- tances and thus the high frequency impedance of the path. high speed currents in an inductive ground return will create an unwanted voltage noise. broad ground plane areas will reduce the parasitic inductance. input capacitance along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. even 1 pf or 2 pf of capacitance will reduce the input imped- ance at high frequencies, in turn increasing the amplifier?s gain, causing peaking of the frequency response or even oscillations if severe enough. it is recommended that the external passive com- ponents that are connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. the ground and power planes must be kept at a distance of at least 0.05 mm from the input pins on all layers of the board. output capacitance to a lesser extent, parasitic capacitances on the output can cause peaking of the frequency response. there are two methods to effectively minimize its effect: 1. put a small value resistor in series with the output to isolate the load capacitance from the amplifier?s output stage. (see tpc 7.) 2. increase the phase margin by (a) increasing the amplifier?s gain or (b) adding a pole by placing a capacitor in parallel with the feedback resistor. input-to-output coupling to minimize capacitive coupling, the input and output signal traces should not be parallel. this helps reduce unwanted posi- tive feedback. external components and stability the AD8007 and ad8008 are current feedback amplifiers and, to a first order, the feedback resistor determines the bandwidth and stability. the gain, load impedance, supply voltage, and input impedances also have an effect. tpc 6 shows the effect of changing r f on bandwidth and peaking for a gain of +2. increasing r f will reduce peaking but also reduce the bandwidth. tpc 1 shows that for a given r f , increasing the gain will also reduce peaking and bandwidth. table i shows the recommended r f and r g values that optimize bandwidth with minimal peaking. table i. recommended component values gain r f ( )r g ( )r s ( ) e1 499 499 200 +1 499 na 200 +2 499 499 200 +5 499 124 200 +10 499 54.9 200 the load resistor will also affect bandwidth as shown in t pcs 2 and 5. a comparison between tpcs 2 and 5 also demonstrates the effect of gain and supply voltage. when driving loads with a capacitive component, stability is improved by using a series snub resistor r snub at the output. the frequency and pulse responses for various capacitive loads are illustrated in tpcs 7 and 42, respectively. for noninverting configurations, a resistor in series with the input, r s , is needed to optimize stability for gain = +1, as illustrated in tpc 3. for larger noninverting gains, the effect of a series resistor is reduced.
rev. d ?6 AD8007/ad8008 outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa 5-lead thin shrink small outline transistor package [sc70] (ks-5) dimensions shown in millimeters 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 0.22 0.08 0.46 0.36 0.26 3 5 4 1 2 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203aa
rev. d AD8007/ad8008 e17e revision history location page 6/03?data sheet changed from rev. c to rev. d change to layout considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 deleted figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 deleted evaluation board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10/02?data sheet changed from rev. b to rev. c connection diagrams captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ordering guide updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9/02?data sheet changed from rev. a to rev. b. updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8/02?data sheet changed from rev. 0 to rev. a. added ad8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal added soic-8 (rn) and msop-8 (rm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to maximum power dissipation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 new figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 new tpcs 19e24 and tpcs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to evaluation board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 msop-8 (rm) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
e18e
e19e
c02866e0e6/03(d) e20e

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